1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a circuit board having a semiconductor chip embedded therein.
2. Description of the Prior Art
With electronic products becoming smaller, thinner, and more compact, a typical package substrate for carrying a semiconductor chip or electronic components has to be downsized. Semiconductor manufacturers developed various packages, and one of which is ball grid array (BGA). An advanced semiconductor package technology, BGA enables more I/O connections to be provided in a unit area of a package substrate so as to meet requirements for integration of a semiconductor chip.
However, with a conventional BGA semiconductor package, a semiconductor chip is adhered to a package substrate and then undergoes wire bonding, or a semiconductor chip is flip-chip-connected to a package substrate before solder balls are implanted on the back of the package substrate for electrical connection. In so doing, BGA achieves a high pin number and yet causes drawbacks: during high-frequency or high-speed operation, wires with long conduction paths prevent enhancement of electric characteristics and thereby restrict performance; and performing the step of interface connecting repeatedly incurs high manufacturing costs.
To efficiently enhance electric quality and meet the demand for products of the next generation, manufacturers endeavor to study how to embed a semiconductor chip in a package substrate to enable direct electrical connection so as to shorten a path of electrical conduction, reduce signal loss and signal distortion, and enhance performance during high-speed operation.
Referring to FIG. 1A through FIG. 1G, schematic views of a conventional circuit board having a semiconductor chip embedded therein during a fabrication process thereof are shown.
Referring to FIG. 1A, a substrate body 10 is provided. The substrate body 10 has a first surface 10a, an opposing second surface 10b, and a through-hole 100 disposed in the substrate body 10 to penetrate the first surface 10a and the second surface 10b. A first core circuit layer 101 and a second core circuit layer 102 are disposed on the first surface 10a and the second surface 10b, respectively. A plurality of conductive vias 103 are disposed in the substrate body 10 to penetrate the first surface 10a and the second surface 10b and thereby electrically connect the first core circuit layer 101 and the second core circuit layer 102. A semiconductor chip 11 is received in the through-hole 100. The semiconductor chip 11 has an active surface 11a and an opposing inactive surface 11b. A plurality of electrode pads 111 are provided on the active surface 11a 
Referring to FIG. 1B, a first dielectric layer 12a made of resin clad copper foil (RCC) and provided with a first metal layer 13a thereon is laminated to the active surface 11a of the semiconductor chip 11 and the first surface 10a of the substrate body 10, and a second dielectric layer 12b made of resin clad copper foil (RCC) and provided with a second metal layer 13b thereon is laminated to the inactive surface 11b of the semiconductor chip 11 and the second surface 10b of the substrate body 10. The first dielectric layer 12a and the second dielectric layer 12b fill the through-hole 100 so as for the semiconductor chip 11 to be fixed in position to the through-hole 100.
Referring to FIG. 1C, a plurality of first apertures 120a corresponding in position to the electrode pads 111 on the semiconductor chip 11 are disposed in the first dielectric layer 12a and the first metal layer 13a by laser drilling so as for a portion of the surface of the electrode pads 111 to be exposed. Likewise, a plurality of second apertures 120b corresponding in position to a portion of the second core circuit layer 102 are disposed in the second dielectric layer 12b and the second metal layer 13b by laser drilling so as for a portion of the second core circuit layer 102 to be exposed to thereby form electrically connected to pads 102a. 
Referring to FIG. 1D, a first conductive layer 14a is disposed on the first metal layer 13a, the inner wall of the first apertures 120a, and a portion of the electrode pads 111. Likewise, a second conductive layer 14b is disposed on the second metal layer 13b, the inner wall of the second apertures 120b, and a portion of electrically connected to pads 102a. 
Referring to FIG. 1E, disposed on the first conductive layer 14a is a first resist layer 15a provided with a plurality of first opening areas 150a for exposing a portion of the first conductive layer 14a. Likewise, disposed on the second conductive layer 14b is a second resist layer 15b provided with a plurality of second opening areas 150b for exposing a portion of the second conductive layer 14b. 
Referring to FIG. 1F, a first circuit layer 16a and a second circuit layer 16b are disposed on the exposed portions of the first conductive layer 14a and the second conductive layer 14b exposed from the first opening areas 150a and the second opening areas 150b, respectively, and disposed in the first apertures 120a are a plurality of first conductive vias 161a for electrically connecting with the electrode pads 111 on the semiconductor chip 11. Likewise, disposed in the second apertures 120b are a plurality of second conductive vias 161b for electrically connecting with pads 102a. 
Referring to FIG. 1G, the first conductive layer 14a and the first metal layer 13a beneath the first resist layer 15a are removed to expose the first circuit layer 16a and the first dielectric layer 12a. Likewise, the second resist layer 15b and the second conductive layer 14b and the second metal layer 13b beneath the second resist layer 15b are removed to expose the second circuit layer 16b and the second dielectric layer 12b. 
Embedding the semiconductor chip 11 in the through-hole 100 solves problems arising from a long path of electrical conduction of a wire of the prior art, but the first metal layer 13a completely covers the first dielectric layer 12a and thereby covers an alignment target of the semiconductor chip 11, and in consequence during a process of forming the first apertures 120a in the first metal layer 13a and the first dielectric layer 12a by laser drilling, the first metal layer 13a affects the standard alignment of laser drilling and therefore compromises the preciseness in positioning the aperture; as a result, it is difficult to accurately align the first apertures 120a with the electrode pads 111 on the semiconductor chip 11, respectively. This has an unfavorable effect on electrical connection of the electrode pads 111 and the first conductive vias 161a subsequently provided in the first apertures 120a, and thus reliability of electrical connection is compromised.
The first circuit layer 16a is disposed on the first dielectric layer 12a. On the first metal layer 13a, a metal layer is provided by plating the first circuit layer 16a to the first conductive layer 14a and then by removing the first resist layer 15a and the first conductive layer 14a and the first metal layer 13a beneath the first resist layer 15a by chemical etching. However, removing the first conductive layer 14a and the first metal layer 13a otherwise covered by the first resist layer 15a causes the line-width side of the first circuit layer 16a to be removed by etching. Hence, it is necessary to allow for a relatively large line width of the first circuit layer 16a so as to avoid etching. In so doing, reduction of the line width and pitch of the first circuit layer 16a is infeasible to the detriment of a high-density layout.
In addition, owing to advancement of technology, to meet the demand for multiplexing and high-frequency functionality, the electrode pads 111 on the semiconductor chip 11 are becoming closer to each other, wherein the electrode pads 111 comprise power pads and signal pads. If the signal pads are too close to each other, noise will be generated as a result of interference from between the semiconductor chips 11 in high-frequency operation, thus resulting in signal distortion and deterioration of electric performance.
Accordingly, manufacturers are confronted with an urgent issue that involves providing a semiconductor package having a semiconductor chip embedded therein with a view to overcoming drawbacks of the prior art, namely: a circuit is made from a metal layer that affects an alignment target, and thus conductive vias in the circuit layer are unlikely to be electrically connected to the electrode pads on the semiconductor chip accurately; the conventional circuit layer does not feature fine pitches and therefore is unfavorable for a high-density layout; and during high-frequency operation of the semiconductor chip, closely-provided signal pads bring about interference-induced noise, thus resulting in signal distortion and deterioration of electric performance.